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ICS557-08
2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS
Description
The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input pairs and fan out to one pair of differential HCSL or LVDS outputs. This chip is suited especially for PCI-Express applications, where there is a need to select the PCI-Express clock either locally from the PCI-E card or from the motherboard.
Features
* * * * *
Packaged in 16-pin TSSOP Available in Pb (lead) free package Operating voltage of 3.3 V Low power consumption Input clock frequency of up to 200 MHz for HCSL and up to 100 MHz for LVDS
* Jitter 60 ps (cycle-to-cycle)
Block Diagram
VDD 3
OE
IN1 IN1 IN2 IN2 CLK MUX 2 to 1 CLK
3 SEL GND PD
Rr (IREF)
MDS 557-08 C I n t e gra te d C i r c u i t S y s t e m s
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525 Race Stre et, San Jo se, CA 9 5126
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Pin Assignment
VDD IN1 IN1 PD IN2 IN2 OE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL CLK CLK GND GND VDD VDD IREF
Select Table
SEL 0 1 Input Pair selected IN2/ IN2 IN1/ IN1
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
VDD IN1 IN1 PD IN2 IN2 OE GND IREF VDD VDD GND GND CLK CLK SEL
Pin Type
Power Input Input Input Input Input Input Power Output Power Power Power Power Output Output Input HCSL/LVDS true input signal 1.
Pin Description
Connect to +3.3 V. Supply voltage for Input clocks. HCSL/LVDS complimentary input signal 1. Powers down the chip and tri-states outputs when low. Internal pull-up resistor. HCSL/LVDS true input signal 2. HCSL/LVDS complimentary input signal 2. Provides output or, tri-states output (High = enable outputs; Low = disable). Internal pull-up resistor. Connect to ground. Precision resistor attached to this pin is connected to the internal current reference. Connect to +3.3 V. Supply Voltage for Output Clocks. Connect to +3.3 V. Supply Voltage for Output Clocks. Connect to ground. Connect to ground. HCSL/LVDS Complimentary output clock . HCSL/LVDS True output clock. SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS557-08 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane.
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 F should be connected between VDD and GND pins as close to the device as possible.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50, then Rr = 475 (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS557-08. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Load Resistors RL
Since the clock outputs are open source outputs, 50 external resistors to ground are to be connected at each clock output.
Output Termination
The PCI-Express differential clock outputs of the ICS557-08 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-08 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section.
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Output Structures
IREF =2.3 mA 6*IREF
R R 475
See Output Termination Sections - Pages 3 ~ 5
General PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-08.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch inch ohm ohm Unit inch inch Unit inch inch
PCI-Express Device Routing
L1 RS L1' RS
L2 L2' RT L3' RT L3
L4 L4'
ICS557-08 Output Clock
PCI-Express Load or Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0 tOR
500 ps
500 ps
tOF 0.525 V 0.175 V
0.525 V 0.175 V
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. RP RQ RT L3 length, Route as coupled 50 ohm differential trace. L3 length, Route as coupled 50 ohm differential trace. Dimension or Value 0.5 max 0.2 max 100 100 150 Unit inch inch ohm ohm ohm
LVDS Device Routing
L1 RQ L1'
L3 L3'
RP
RT ICS557-08 Clock Output
L2' L2
RT LVDS Device Load
Typical LVDS Waveform
1325 mV
1000 mV tOR 500 ps 500 ps tOF
1250 mV 1150 mV
1250 mV 1150 mV
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-08. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Protection (Input) 7V
Rating
-0.5 V to VDD+0.5 V -40 to +85C -65 to +150C 125C 260C 2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C Parameter Supply Voltage Input High Voltage
1
Symbol V VIH VIL IIL IDD IDDOE IDDPD
Conditions OE, SEL, PD OE, SEL, PD 0 < Vin < VDD 50, 2 pF OE =Low No load, PD =Low Input pin capacitance Output pin capacitance CLK outputs OE, SEL, PD
region.
Min. 3.135 2.0 VSS-0.3 -5
Typ.
Max. 3.465 VDD +0.3 0.8 5 40 20 400 7 6 5
Units V V V A mA mA A pF pF nH k k
Input Low Voltage1 Input Leakage Current2 Operating Supply Current
Input Capacitance Output Capacitance Pin Inductance Output Resistance Pull-up Resistor
CIN COUT LPIN ROUT RPUP
3.0 110
1 Single edge is monotonic when transitioning through 2 Inputs with pull-ups/-downs are not included.
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
AC Electrical Characteristics Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85C Parameter Operating Frequency Input High Voltage Input Low Voltage Differential Input Voltages Input Offset Voltage Output High Voltage Output Low Voltage Crossing Point Voltage1,2 Crossing Point Voltage1,2,4 Jitter, Cycle-to-Cycle1,3 Rise Time
1,2 1,2 1,2 1,2
Symbol
Conditions HCSL termination LVDS termination
Min.
Typ.
Max. 200 100
Units MHz MHz mV mV mV V mV mV mV mV ps
VIH VIL (VID) (VIS) VOH VOL
HCSL HCSL LVDS LVDS HCSL HCSL Absolute Variation over all edges
660 -150 250 1.125 660 -150 250
700 0 350 1.25 700 0 350
850 450 1.375 850 550 140
1,2
60 tOR tOF From 0.175 V to 0.525 V From 0.525 V to 0.175 V 175 175 332 344 700 700 125 45 55 10 10 3.0 4
ps ps ps % s s ms ns
Fall Time1,2 Rise/Fall Time Variation1,2 Duty Cycle1,3 Output Enable Time Stabilization Time Input to Output Delay
5
All outputs All outputs tSTABLE From power-up VDD=3.3 V Input differential clock to output differential clock delay measured at crossing point of input levels to crossing point of output levels
Output Disable Time5
1 2 3 4 5
Test setup is RL=50 ohms with 2 pF, Rr = 475 (1%). Measurement taken from a single-ended waveform. Measurement taken from a differential waveform. Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal. CLK and CLK pins are tri-stated when OE is Low asserted. CLK and CLK are driven differential when OE is High unless its PD = low.
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
93 78 65 20
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Marking Diagram (ICS557G-08)
16 9
Marking Diagram (ICS557GI-08)
16 9
557G-08 ###### YYWW$$
1 8
557GI-08 ###### YYWW$$
1 8
Marking Diagram (ICS557G-08LF)
16 9
Marking Diagram (ICS557GI-08LF)
16 9
557G08LF ###### YYWW
1 8 1
557GI08L ###### YYWW
8
Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. "LF" denotes Pb free package. 4. "I" denotes industrial temperature device 5. Bottom marking: (origin). Origin = country of origin if not USA.
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters Symbol Min Max
Inches* Min Max
E1 INDEX AREA
E
12 D
A A1 A2 b C D E E1 e L aaa
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004
A2 A1
A
*For reference only. Controlling dimensions in mm.
c
-Ce
b SEATING PLANE L
aaa C
Ordering Information
Part / Order Number
ICS557G-08 ICS557G-08T ICS557G-08LF ICS557G-08LFT ICS557GI-08 ICS557GI-08T ICS557GI-08LF ICS557GI-08LFT See Page 9 See Page 9
Marking
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 557-08 C In te grated Circuit Systems
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525 Ra ce Street, San Jose, CA 9512 6
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ICS557-08
2:1 Multiplexer Chip for PCI-Express
Revision History
Rev.
C
Originator
D.Chan
Date
02/16/06
Description of Change
Added industrial temp range; updated PCI-Express Waveform diagram to include 0.525 V; changed "Supply Voltage, VDD" spec in Absolute Max. Ratings from 5.5 V to 7 V; changed CLKOUT to CLK and CLK ; added marking diagrams for I-temp device.
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